1. Field of the Invention
The present invention relates to a method of forming a gate structure, and more specifically, to a method capable of avoiding word line/bit line short-circuiting.
2. Description of the Prior Art
Dynamic random access memory (DRAM) is composed of many memory cells, and each memory cell has a metal oxide semiconductor (MOS) transistor and a capacitor. The gate of the MOS transistor (also known as word line) serves as a switch of the MOS transistor, while the drain or the source is connected to a bit line for writing and erasing data.
Please refer and FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are schematic diagrams illustrating a conventional method of forming a gate structure. As shown in FIG. 1, primarily, a substrate 10 having at least a stacked gate structure 12 is provided. The stacked gate structure 12 from bottom to top comprises a gate oxide layer 14, a polysilicon layer 16, a silicide layer 18, and a cap layer 20.
Then as shown in FIG. 2, a chemical vapor deposition (CVD) process is performed to deposit a silicon nitride layer (not shown) onto the substrate 10. Following that, an anisotropic etching process is performed to remove a portion of the silicon nitride layer (not shown) to form a spacer 22 on the sidewalls of the stacked gate structure 12. Finally, an implantation process is performed to form a drain (not shown) and a source (not shown) in the substrate 10.
The conventional method further comprises the steps of forming a bit line after forming the stacked gate structure 12. Please refer to FIG. 3 to FIG. 5. FIG. 3 to FIG. 5 are schematic diagrams showing the steps of forming the bit line. As shown in FIG. 3, first a barrier layer 24 is deposited onto the substrate 10 and the stacked gate structure 12. Then a borophosphosilicate glass (BPSG) layer 26 is deposited on the barrier layer 24, and a flow process is performed for planarizing the BPSG layer 26. Finally a chemical mechanical polishing (CMP) process is performed to remove the BPSG layer 26 higher than the cap layer 20.
The material of the barrier layer 24 is silicon nitride, which is capable of preventing the ions of BPSG layer 26 from diffusing into the substrate 10 in the flow process.
As shown in FIG. 4, a dielectric layer 28, such as an oxide layer using TEOS as precursor, is deposited onto the stacked gate structure 12. Then a photo-etching process is performed to remove a portion of the dielectric layer 28, the BPSG layer 26, and the barrier layer 24 for forming a contact hole 30.
Finally as shown in FIG. 5, a bit line 32 is formed for electrically connecting to the drain or source (not shown) of the substrate 10 via the contact hole 30.
It can be seen from the above description that the conventional method utilizes the spacer 22 to avoid the word line (the polysilicon layer 16 and the silicide layer 18)/bit line short-circuit problem. However, as semiconductor device integrity increases and critical dimension decreases, the spacer 22 is apt to be destroyed in the step of forming the contact hole 30. As shown in FIG. 4, the bit line 32 and the silicide layer 18 will be short-circuited easily under this condition. Particularly, when critical dimension is under 0.11 μm, the short-circuit problem is not ignorable.